1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly, to semiconductor integrated circuits having row decoders capable of timing control.
2. Description of the Related Art
Generally, an image sensor captures an image by using an optical sensing semiconductor element. The image sensor usually includes a pixel array with transistors and several sensing elements, such as photodiodes. The image sensor receives light from objects and generates an electrical image signal. An image sensor manufactured using Complementary Metal Oxide Semiconductor (“CMOS”) techniques is called a CMOS image sensor.
FIG. 1 shows a block diagram illustrating a conventional CMOS image sensor. Referring to FIG. 1, a CMOS image sensor 100 includes an active pixel sensor (“APS”) array 110, a row decoder 120, a row driver 130, a correlated double sampling and digital converting (“CDS&ADC”) unit 140, a column decoder 150 and a CMOS image sensor (“CIS”) controller 160. The APS array 110 is provided with active pixel sensors arranged thereon. A predetermined active pixel in the APS array 110 is addressed through the row decoder 120 and the column decoder 150. The CDS&ADC unit 140 samples data of the active pixel under the control of the CIS controller 160 and operates to obtain high quality images.
FIG. 2 shows a schematic diagram of a unit pixel 200, and FIG. 3 shows a relevant timing diagram 300. Operation of the unit pixel 200 may be better understood with reference to the timing diagram 300. The unit pixel 200 includes a reset transistor MR, a transmitting transistor MT, a driver transistor MD and a selection transistor MS. Initially, the reset transistor MR is turned on in response to a high level of a reset gate signal RG so that a floating diffusion node FD is pre-charged to a high level. The driver transistor MD is turned on in response to a high level of the floating diffusion node FD and the selection transistor MS is turned on in response to a high level of a selection gate signal SEL so that an output node OUT gets to be a high level called the first level. The reset transistor MR is turned off in response to a low level of a reset gate signal RG so that the output node OUT becomes high level called the second level. After that, if the transmitting transistor MT is turned on in response to the transmitting gate signal TG, the output node OUT falls to a third level. The difference between the second level and the third level of the output node OUT is outputted as an actual image data signal.
FIG. 4 illustrates voltage variations 400 of a photodiode PD and a floating diffusion node FD based on the cross-section of the unit pixel 200 shown in FIG. 2. Reference indicia “i” indicates the initial state when the reset gate signal RM is high level. Reference indicia “ii” indicates that the well of the photodiode PD is emptied in response to the high level of the transmitting gate signal TG by shuttering operation. Reference indicia “iii” indicates that the potential of the transmitting gate is raised in response to the low level of the transmitting gate signal TG after shuttering. Reference indicia “iv” indicates that the photodiode PD integrates the light. Reference indicia “v” indicates that the potential of the reset gate is raised in response to the low level of the reset gate signal RG. Reference indicia “vi” indicates that the potential of the transmitting gate is lowered in response to the high level of the transmitting gate signal TG and the potential of the sensing node FD is changed. The variation of the potential of the floating diffusion node FD is an image data signal and then the CDS is performed to sample image data.
FIG. 5 shows a schematic diagram of a general circuit of the row decoder 120 of FIG. 1. Referring to FIG. 5, an i-th row reset gate signal RGi, an i-th transmitting gate signal TGi, an i-th selection gate signal SELi, an i+1st row reset gate signal RGi+1, an i+1st transmitting gate signal TGi+1, an i+1st selection gate signal SELi+1, an i+2nd row reset gate signal RGi+2, an i+2nd transmitting gate signal TGi+2, and an i+2nd selection gate signal SELi+2 are generated by the combination of row address signals Ai, Ai+1, and Ai+2, a transmitted signal TX, a selection signal SEL and a reset signal RX.
FIGS. 6A and 6B illustrate operation waveforms 600 and 610, respectively, of unit cells connected to two rows and one column, such as unit cells connected to the p-th row and the q-th row, respectively. If the unit cell connected to the p-th row performs CDS operation as shown in FIG. 6A, the unit cell connected to the q-th cell represents integration operation of the photodiode as shown in FIG. 6B. In other words, the integration operation of the q-th row is performed during the time 1H−CDS that results from subtracting the CDS operation of the p-th row from the 1H time representing the period of horizontal synchronization signal HSYNC.
FIG. 7 illustrates an example of row addressing for frame data, indicated generally by the reference numeral 700. Referring to FIG. 7, the first to third frame data are inputted in accordance with a vertical synchronization signal VSYNC. Suppose that ten row addresses 0 to 9 are set for one frame data. The row shutter value cintr determines the shutter exposure time, is stored in a register of CIS controller 160 shown in FIG. 1, and controls the shuttering operation. The row address that is shuttered if the row shutter value is two is inputted before the CDS row address by two rows and shutters the unit cells connected to the corresponding addresses so that the integration operation is performed. The first frame data are matched to shutter row addresses 0 to 9 and CDS row addresses 0 to 9, and the image data signals of the selected unit cells are transferred to the CDS&ADC unit 140 of FIG. 1 without any losses. This operation is performed as represented by the timing chart shown in FIG. 8.
Referring to FIG. 8, a timing chart is indicated generally by the reference numeral 800. During the first 1H time, the CDS operation is performed for the 0th row address and the shuttering operation is performed for the 2nd row address. During the second 1H time, the CDS operation is performed for the first row address and the shuttering operation is performed for the third row address. During the third 1H time, the CDS operation is performed for the second row address at which shuttering operation is performed during the first 1H time.
However, if the CDS operation and the shuttering operation are performed using the decoder 120 shown in FIG. 5, the following problems can be found. Referring to FIG. 7, if the row shutter value cintr is set be 7, only the shutter row addresses 0 to 4 are addressed for the second frame data and the shuttering operation is performed, but the shuttering operation is not performed for the remaining shutter row addresses 5 to 9. This is because the shutter row addresses 0 to 9 for the third frame are inputted in accordance with a shutter synchronization signal SHSYNC to satisfy the row shutter value cintr=7 for the following third frame. The third frame is matched to shutter row addresses 0 to 9 and CDS row addresses 0 to 9 and the image data signals of the selected unit cells are transferred to CDS&ADC unit 140 of FIG. 1 without any losses. Here, the data of the unit cells corresponding to the fifth to ninth addresses of the second frame are transferred to the CDS&ADC unit 140 without the long time shutter exposure of the row shutter value cintr=7. This causes the problem that the second frame data become invalid data.
Accordingly, what is needed is a row decoder for a CMOS image sensor that can control exposure time without increasing the layout area.